1. Field of the Invention
The present invention is in the field of integrated circuit fabrication. More particularly, the invention is in the field of fabrication of damascene interconnects for integrated circuits using copper and low dielectric constant materials.
2. Background Art
The drive to fabricate faster IC (Integrated Circuit) chips is in large part focused on improving the speed of the IC chip interconnect while maintaining or improving other aspects of IC chip performance such as low noise and long term reliability. Interconnect delay is directly proportional to the product of interconnect resistance and the capacitance driven by the interconnect. Thus, in order to improve the speed of the IC chip interconnect, there is need to the reduce the resistivity and the capacitance of the IC chip interconnect. The capacitance of the interconnect is directly proportional to the dielectric constant (xe2x80x9ckxe2x80x9d) of the dielectric that insulates the interconnect from other interconnect or other circuits of the IC chip. As such, reducing the dielectric constant of the dielectric results in a reduction of the interconnect capacitance and a reduction in the interconnect delay.
Traditionally, aluminum has been used as the primary interconnect conductor and silicon oxide has been used as the primary dielectric in IC chips. Recently, copper has become more desirable as an interconnect conductor at least partly due to the fact that copper has lower resistivity than aluminum. Also recently, a number of low dielectric constant (xe2x80x9clow-kxe2x80x9d) materials having dielectric constants below that of silicon oxide have been used in IC chips (silicon oxide has a dielectric constant of approximately 4.0). However, the use of copper and low-k dielectric materials has introduced a number of challenges in manufacturing IC chips.
For example, it is difficult to etch copper and as such the xe2x80x9csubtractive etchxe2x80x9d process used to etch aluminum cannot be successfully used in copper chips. Thus, the present approach to patterning copper interconnect is based on xe2x80x9cdamascenexe2x80x9d processing. The term xe2x80x9cdamascenexe2x80x9d is derived from the ancient in-laid metal artistry originated in Damascus. According to the damascene process, a trench or canal is cut into the dielectric and then filled with metal. FIGS. 1A through 1D help describe an overview of the damascene process used to fabricate copper interconnect.
Referring to FIG. 1A, insulating layer 102 (for example, silicon oxide) is formed on a substrate 104, which usually contains circuitry and may contain other interconnection levels. To help with the patterning of copper by the damascene process, layer 102 should have a uniform thickness and be as flat as possible. An ideally flat insulating layer 102 is shown in FIG. 1A.
FIG. 1B shows a cross-section of layer 102 after patterning to create two trenches, wide trench 106 and narrow trench 108. These trenches are formed by removing a top portion of layer 102 using photolithography and a suitable anisotropic etch technique, such as reactive ion etching, which are known in the art. These trenches are where copper interconnect conductors should be laid in. Moreover, the part of layer 102 which is situated between wide trench 106 and narrow trench 108 provides insulation between the copper interconnect to be laid in trench 106 and the copper interconnect to be laid in trench 108. This part of layer 102 is referred to by numeral 107. Referring to FIG. 1C, copper film 112 is shown as having been deposited over insulating layer 102. Although not shown in any of the FIGURES, prior to deposition of copper film 112, a metal barrier layer such as tantalum (Ta) or tantalum nitride (TaN) is deposited over insulating layer 102. Further, a physical vapor deposition (PVD) copper seed layer (not shown in any of the FIGURES) may also be deposited. Copper film 112 may, for example, be formed by chemical vapor deposition (CVD), PVD, PVD followed by reflow, or electroplating. Preferably, copper film 112 is deposited to a depth such that trenches 106 and 108 are completely filled with copper. Manifestly, the unwanted portions of copper film 112, for example the portion that is shown as covering part 107 of layer 102, must be removed.
FIG. 1D shows a wide inlaid copper conductor 114 and a narrow inlaid copper interconnect 116 remaining in trenches 106 and 108, respectively, after polishing to remove the unwanted portions of copper film 112. Polishing is preferably accomplished by chemical-mechanical polishing (xe2x80x9cCMPxe2x80x9d), wherein the semiconductor wafer and/or a polishing pad are rotatably mounted and brought into contact with each other under rotation. A slurry providing both abrasive and chemically reactive components is supplied, typically to the pad, during polishing. The abrasive component is typically comprised of finely ground colloidal silica or alumina particles. The chemically reactive component is typically diluted acid and/or hydrogen peroxide, with the remainder of the slurry comprised of deionized water. In general, it is desirable that the slurry composition and polishing conditions (e.g. rotational velocity, polish force, temperature) be adjusted such that the conducting films (i.e. the deposited copper film and the metal barrier layer) are selectively removed at a faster rate than the insulating layer (30:1 being a typical ratio) during the CMP.
One drawback of the CMP process, however, is illustrated in FIG. 1D. The top surface of narrow copper interconnect 116 is shown as slightly xe2x80x9cdishedxe2x80x9d but substantially co-planar with the upper surface of insulating layer 102. However, wide copper interconnect 114 is shown as severely dished. This effect is referred to as xe2x80x9cdishingxe2x80x9d in the present application. The dishing phenomenon, such as that shown in wide interconnect 114, results in an uneven profile in the interconnect layer which, among other things, is harmful to the fabrication process of subsequent layers in the IC chip. In extreme cases, sections of a wide conductor, such as wide conductor 114, may be completely removed from the trench during polishing, leaving the trench bottom exposed. This total absence of any metal at the central parts of a wide metal conductor is undesirable since, for example, it causes an increase in the resistance of the metal interconnect and also reduces the long term reliability of the IC chip.
In addition to the harmful effects on the fabrication process of subsequent layers in the IC chip, dishing detrimentally affects electrical performance characteristics of the copper interconnects. Copper dishing results in a non-uniform thickness of copper interconnects. As a result of this non-uniform thickness of the copper interconnects the electrical performance characteristics are negatively affected. For example, the resistivity of a copper interconnect is a function of its thickness and as such, the resistivity of a copper interconnect is negatively affected due to non-uniform thickness of the copper interconnect. As another example, the amount of current that a copper interconnect can conduct is dependent on the thickness of the interconnect. A lower thickness results in a more pronounced electromigration problem when high currents are passed through the interconnect. Electromigration results in a loss of metal at certain points in the interconnect which would then result in a reliability problem. Thus, a non-uniform thickness in the copper interconnect may decrease electromigration performance and cause reliability problems.
Another drawback of the CMP process is also illustrated in FIG. 1D. The sharp edges of insulating layer 102 at the top of the walls in wide trench 106 and narrow trench 108 shown in FIG. 1C have been rounded by the CMP process. An example of such rounding effect is pointed to by numeral 115 in FIG. 1D. This rounding of the sharp edges of insulating layer 102 at the top of the trench walls and subsequent loss of oxide thickness in dense narrow trench arrays (not shown in FIG. 1D) is referred to in the present application as xe2x80x9cdielectric erosion.xe2x80x9d Dielectric erosion is harmful to the integrity of the IC chip and negatively affects the fabrication process of subsequent layers in the IC chip.
One method known in the art to reduce copper dishing and dielectric erosion involves a two-step or a multi-step copper CMP process. In the first step, the unwanted portions of the copper situated above the dielectric are removed using CMP slurry chemistries and process parameters designed to quickly remove copper. In the second step, the slurry chemistries and parameters are chosen such that the removal rate for copper and the oxide dielectric surrounding the copper are about equal and a specific amount of oxide is removed for a given time period. As explained in a paper entitled xe2x80x9cPlanarization of Dual-Damascene Post-Metal-CMP Structuresxe2x80x9d by Chenting Lin, Larry Clevenger, Florian Schnabel, Fen Jamin, and David Dobuzinski published in the Proceedings of the 1999 International Interconnect Technology Conference, page 87, May 1999, this second step aims to planarize the overall surface of the wafer, reducing the effects of copper dishing and dielectric erosion. However, according to this known method, it is difficult to remove the exact required quantities of dielectric to accomplish the desired planarization.
U.S. Pat. No. 5,578,523 entitled xe2x80x9cMethod for forming inlaid interconnects in a semiconductor devicexe2x80x9d discloses a method for forming an inlaid interconnect by chemical mechanical polishing. A polish assisting layer is formed between an interlayer dielectric and an interconnect metal. The polish assisting layer is removed at approximately the same rate as the interconnect metal during the final stages of polishing and therefore dishing is avoided.
U.S. Pat. No. 5,534,462 entitled xe2x80x9cMethod For Forming A Plug And Semiconductor Device Having The Samexe2x80x9d discloses a method for forming a plug in a semiconductor device. An aluminum nitride glue layer is deposited on an interlayer dielectric. A contact opening is then formed. Tungsten or other plug material is then deposited in the opening and on the glue layer and afterward polished or etched back to form the plug.
U.S. Pat. No. 5,064,683 entitled xe2x80x9cMethod For Polish Planarizing A Semiconductor Substrate By Using A Boron Nitride Polish Stopxe2x80x9d discloses a polish planarization method using a boron nitride polish stop layer. The stop layer is deposited over a substrate. A dielectric or conductive material is deposited over the stop layer and the recessed regions of the substrate. The dielectric or conductive material is then polished back until the stop layer is reached.
U.S. Pat. No. 4,789,648 entitled xe2x80x9cMethod For Producing Coplanar Multi-Level Metal/Insulator Films On A Substrate And For Forming Patterned Conductive Lines Simultaneously With Stud Viasxe2x80x9d discloses a method for forming multiple levels of patterned conductive lines connected by stud vias through insulation layers. As part of the fabrication process an etch stop material is used to assist in defining desired wiring channels.
U.S. Pat. No. 4,936,950 entitled xe2x80x9cMethod Of Forming A Configuration Of Interconnections On A Semiconductor Device Having A High Integration Densityxe2x80x9d discloses a method for forming multi-level interconnects using conductive contact studs. The layers of interconnect are separated by isolating layers. As part of this process, a separation layer is used which can be selectively removed with respect to the isolation layers.
U.S. Pat. No. 5,225,372 entitled xe2x80x9cMethod Of Making A Semiconductor Device Having An Improved Metallization Structurexe2x80x9d discloses a method for fabricating semiconductor device interconnects that uses a conductive layer with an underlying diffusion barrier metal attached to a doped glass layer by an intermediate metal adhesion layer.
U.S. Pat. No. 5,272,117 entitled xe2x80x9cMethod For Planarizing A Layer Of Materialxe2x80x9d discloses a method for forming a planarized layer of material using an etch stop layer to accurately determine the thickness of the planarized layer.
The above-discussed paper and patents have not overcome a number of problems inherent in the CMP process. Some of the methods described above are not specifically directed to counteracting copper dishing and dielectric erosion. Other methods avoid copper dishing, but leave remnants of the stop layer behind after the mechanical polish is completed. This residual stop layer usually has a higher dielectric constant than the interlayer dielectric, thus increasing the overall capacitance, and as such this residual stop layer is undesirable.
From the above discussion of the background art it is apparent that there is serious need in the art for a method for fabrication of copper interconnects that counteracts the undesirable copper dishing and dielectric erosion effects that are a result of the copper CMP process and at the same time leaves no residual stop layer behind.
The present invention is method for fabrication of damascene interconnects and related structures. The invention counteracts undesirable copper dishing and dielectric erosion effects which would otherwise result from the copper CMP process.
According to the invention, a sacrificial layer is formed over a low-k dielectric. Trenches are then etched inside the sacrificial layer and the low-k dielectric. The trenches are then filled with metal. During a first CMP process, excess metal over the sacrificial layer is removed. During a second CMP process, the sacrificial layer over the low-k dielectric and any remaining excess metal are removed. By the end of the second CMP process substantially all of the sacrificial layer and all of the excess metal are removed. In this manner, the trenches in the low-k dielectric are filled with metal where the metal surface is substantially flush with the surface of the low-k dielectric.